1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing same and more particularly to the semiconductor device composed of a plurality of trench-structured rectangular unit cells.
2. Description of the Related Art
As one of power devices handling comparatively large currents and voltages, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is widely used. The MOSFET has an advantage of requiring no input current to be used for control since it is a voltage control-type device. Moreover, since the MOSFET operates using either of an electron or a hole as a majority carrier and provides no carrier accumulation effects, it has excellent switching characteristics and high resistance against punch-through and therefore is applied to an inductive load such as a switching regulator or a like in many cases.
Instead of an early-type lateral MOSFET designed so as to pass an operating current (drain current) in a horizontal direction on a semiconductor substrate, a vertical MOSFET designed so as to pass the drain current in a vertical direction on the semiconductor substrate is becoming widespread. Since the vertical MOSFET is constructed of a large number of unit cells each being connected in parallel, it is possible to increase current capacity. In addition, a trench-structured vertical type MOSFET in which each unit cell has the trench structure is generally used. In the trench-structured vertical MOSFET, since a channel is formed in the vertical direction along a side face of the trench, not only its excellent applicability to inductive loads is provided but also scale-downs of each cell as well as reduction in channel resistance values are made possible.
FIG. 12 is a top view showing configurations of a conventional trench-structured vertical MOSFET. FIG. 13 is a perspective view of the trench-structured vertical MOSFET of FIG. 12 taken along a line Fxe2x80x94F. As shown in FIG. 12 and FIG. 13, the conventional vertical MOSFET is composed of a plurality of trench-structured rectangular unit cells 59 each including an N-type drain region 53 containing an Nxe2x88x92-type semiconductor layer 52 constructed of an epitaxial layer containing a low impurity concentration (that is, semiconductor layer containing the low impurity concentration) formed on an N+-type semiconductor substrate 51 (that is, semiconductor substrate containing a high impurity concentration), a P-type base region 54 formed by performing an ion implantation on the Nxe2x88x92-type semiconductor layer 52 constituting a part of the N-type drain region 53, a trench surrounding the P-type base region 54 with a depth reaching the Nxe2x88x92-type semiconductor layer 52, a gate electrode 57 made of polysilicon films surrounded by gate oxide films formed within a trench 55 and an N+-type source region 58, with an N-type impurity implanted, having an endless/ring shape formed on a surface of the P-type base region 54 along the trench 55.
A surface of the unit cell 59 is covered with an interlayer dielectric 62 on which a source and base contact aperture section 63 is formed and a source electrode 64, made of, for example, aluminum alloy, is formed so that P-type base region 54 is connected with the N+-type source region 58 through the above aperture section 63. Thus, to allow the trench-structured vertical MOSFET to be applied to inductive loads, it is expected that its channel resistance is reduced and xe2x80x9cresistance property against device breakdownxe2x80x9d is improved. The resistance property against device breakdown represents an index to know how much current flows when a semiconductor device breaks down due to inverse voltages induced between the drain and the source of the MOSFET when connected to the inductive load.
In the conventional MOSFET as shown in FIG. 12 and FIG. 13, in a case where the semiconductor device breaks down due to inverse voltages induced between the drain and the source of the MOSFET when connected to the inductive load, breakdown of the semiconductor device occurs first at cell corner sections 65 in four corners of the unit cell 59 constituting the semiconductor device where the trenches 55 intersect and electric fields concentrate. There is therefore a shortcoming in such conventional MOSFETs that, since breakdown current causes a parasitic bipolar transistor composed of the N-type drain region 53, P-type base region 54 and N+-type source region 58 to be turned ON, the above resistance property against device breakdown is reduced.
A trench-structured vertical MOSFET attempting to prevent such reduction in the resistance property against device breakdown is disclosed in, for example, Japanese Patent Gazette No. 2894820. FIG. 9 is a top view showing configurations of the trench-structured vertical MOSFET disclosed in the above Japanese Patent Gazette. FIG. 10 is a perspective view of the trench-structured vertical MOSFET of FIG. 9 taken along a line Dxe2x80x94D. FIG. 11 is a perspective view of the trench-structured vertical MOSFET of FIG. 9 taken along a line Exe2x80x94E. In the trench-structured vertical MOSFET as shown in FIG. 9 to FIG. 11, a P-type region 66, not the N+-type source region 58, is formed at cell corner sections 65 in four corners of the unit cell 59, where electric fields concentrate. In the trench-structured vertical MOSFET having such configurations, even if the breakdown current flows through current paths xe2x80x9cdxe2x80x9d and xe2x80x9cexe2x80x9d extending from the N-type drain region 53 to a side (channel layer) of the P-type base region 54 and to a surface of the P-type base region 54, since no N+-type source region 58 does not exist in the cell corner sections 65, the parasitic bipolar transistor is not easily turned ON, thus enabling improvement of a resistance property against device breakdown. Moreover, in FIG. 9 to FIG. 11, same reference numbers are assigned to same parts as those in FIG. 12 and FIG. 13.
However, the conventional semiconductor device disclosed in the above Japanese Patent Gazette No. 2894820 has a problem in that, since a source region is not formed at cell corner sections of a unit cell, a channel layer is not formed at the cell corner sections, causing an increase in channel resistance. That is, in the semiconductor device shown in the above Japanese Patent Gazette, since no source region 58 exists in the cell corner sections 65, the resistance property against device breakdown can be improved, however, extension of the path of the planar channel layer ends in the cell corner sections 65, thus causing a small width of the channel layer, resulting in increase in the channel resistance value.
Moreover, in the semiconductor device described above, since no source region 58 exists in the cell corner sections 65, when a cell is to be scaled down, the width of the channel has to be made smaller, which is not suitable for the scale-down of cells.
In view of the above, it is an object of the present invention to provide a semiconductor device having configurations being suitable for scale-down of cells which is capable of, without an increase in channel resistance, improving resistance against device breakdown required when the semiconductor device breaks down due to inverse voltages and a method of manufacturing a same.
According to a first aspect of the present invention, there is provided a semiconductor device having a plurality of trench-structured rectangular unit cells including:
a first conductive type drain region;
a second conductive type base region formed adjacent to the first conductive type drain region;
a trench formed in area surrounding the second conductive type base region;
a gate electrode formed within the trench with a gate insulating film interposed between the gate electrode and the trench;
a first conductive type source region having an endless/ring shape formed along the trench on a surface of the second conductive type base region; and
a region having no source is formed at a center of a rectangular surface of the trench-structured rectangular unit cell and on diagonal lines radially extending from the center of the trench-structured rectangular unit cell.
According to a second aspect of the present invention, there is provided a semiconductor device having a plurality of trench-structured rectangular unit cells including:
a first conductive type drain region;
a second conductive type base region formed adjacent to the first conductive type drain region;
trench formed in area surrounding the second conductive type base region;
a gate electrode formed within the trench with a gate insulating film interposed between the gate electrode and the trench;
a first conductive type source region having an endless/ring shape formed along the trench on a surface of the second conductive type base region; and
a source region narrowing section which partially limits width dimensions on a plane of the first conductive type source region is formed on diagonal lines on a rectangular surface of the trench-structured rectangular unit cell and in a vicinity of the diagonal lines of the trench-structured rectangular unit cell.
In the foregoing, a preferable mode is one wherein the trench-structured rectangular unit cell is coated with an interlayer dielectric in which a source and base contact aperture section are formed and a source electrode is formed through the source and base contact aperture section.
Also, a preferable mode is one wherein the first conductive type source region narrowing section is so structured that the first conductive type source region is narrowed by an arbitrary dimension on diagonal lines of the trench-structured rectangular unit cell in a direction from the source and base contact aperture section in the interlayer dielectric toward a cell corner section.
Also, a preferable mode is one wherein the source region narrowing section is formed at a time of formation of the first conductive type source region after a second conductive semiconductor region containing an impurity concentration being higher than that of the second conductive type base region is formed in advance at a part of a place where the first conductive type source region is to be formed.
According to a third aspect of the present invention, there is provided a method for manufacturing semiconductor devices composed of a plurality of trench-structured rectangular unit cells having steps of forming a second conductive type base region adjacent to a first conductive type drain region, forming trench in area surrounding the second conductive type base region, forming a gate electrode within the trench with a gate insulating film interposed between the gate electrode and the trench, forming a first conductive type source region having an endless/ring shape along the trench on a surface of the second conductive type base region, the method including steps of:
forming the first conductive type drain region by forming a first conductive type semiconductor layer containing an impurity concentration being lower than that of the first conductive type semiconductor layer on a first conductive type semiconductor substrate;
partitioning the first conductive type semiconductor layer into a plurality of unit cells by forming trenches in the first conductive type semiconductor layer existing in area surrounding a place where the second conductive type base region is to be formed;
forming the second conductive type base region on a whole surface of the first conductive type semiconductor layer surrounded by the trenches; and
forming, in a selective order, a first conductive type source region having an endless/ring shape on the surface of the second conductive type base region and a source region narrowing section which limits width dimensions on a plane of the first conductive type source region on diagonal lines on a rectangular surface of the unit cell and in a vicinity of diagonal lines of the unit cell.
In the foregoing, a preferable mode is one wherein, in a first conductive type source region forming process, after a photoresist film patterned so as to have planar shapes of a center portion of the second conductive type base region and of portions formed on diagonal lines extending radially from an area surrounding a center part of the trench-structured rectangular unit cell is formed on the second conductive type base region, a first conductive type impurity is introduced using the photoresist film as a mask.
Also, a preferable mode is one wherein the first conductive type source region forming process is constructed by combining a first impurity introducing process in which, after a first photoresist film patterned to have planar shapes of a center portion of the second conductive type base region and of portions formed on diagonal lines extending radially from the area surrounding the center part of the trench-structured rectangular unit cell is formed on the second conductive type base region, a second conductive type impurity is introduced using the first photoresist film as the mask so that the second conductive semiconductor layer contains an impurity concentration being higher than that of the second conductive] type base region, with a second impurity introducing process in which a second photoresist film patterned to have planar shapes of the center portion of the second conductive type base region and of portions formed on diagonal lines extending radially from the area surrounding the center part of the trench-structured rectangular unit cell is formed on the second conductive type base region, a first conductive type impurity is introduced using the second photoresist film as the mask.
Also, a preferable mode is one wherein a gate electrode forming process in which, after gate insulating film is formed on at least one side face of the trench, a gate electrode is formed within the trench with the gate insulating film interposed between the gate electrode and the trench, is contained between trench forming process and base region forming process.
Furthermore, a preferable mode is one wherein introduction of the first conductive type impurity and the second conductive type impurity in the base region forming process and source region forming process is performed by an ion implantation method.